A customizable logic cell is a prefabricated group of circuit elements that can be combined to perform higher-level logic functions, such as flip-flop functions, specialized logic functions (e.g., XNOR), high output current driver capabilities, and the like. By using customizable logic cells, device designers can create semi-customized integrated circuits more readily and quickly than through the use of conventional ASIC technology. In particular, adding metal layers to configure the customizable logic cell requires fewer production steps than the fabrication of each of the layers for a traditional ASIC device. Generally, integrated circuit designers use traditional customizable logic cells to provide relatively complex functions, but at the expense of a decrease in density of active circuitry. It is common for customizable logic cells to contain circuit elements that do not have individual access. These unused circuit elements constitute waste.
FIG. 1A is a diagram showing a traditional customizable logic cell 100 used to implement a higher-level function. Customizable logic cell 100 includes a number of circuit elements disposed in regions 101, 103 and 105. Specifically, region 101 includes a multiplexer (“M1”) 102, a NAND gate (“N1”) 104, and an inverter (“I1”) 106; region 103 includes a first driver (“D1”) 110 and a second driver (“D2”) 112; and region 105 includes a multiplexer (“M2”) 120, a NAND gate (“N2”) 122, and an inverter (“I2”) 124. FIG. 1A shows customizable logic cell 100 having a specific configuration. In particular, inverter 106 is coupled to multiplexer 102, which, in turn, is coupled to first driver 110, whereas inverter 124 is coupled to multiplexer 120. Noticeably, NAND gate 104, second driver 112, and NAND gate 122 are left unused, all of which contribute to waste as well as a decrease in the density of active circuitry. Moreover, circuit elements 102, 106, 110, 120, and 124 are not individually accessible. Accessing at least one terminal of one of the circuit elements also accesses another circuit element within customizable logic cell 100, thereby precluding the individual access of one without the other. For example, the inputs and/or outputs of the circuit elements in FIG. 1A can be electrically accessed via terminals 140, which may connect to two or more circuit elements, such as is the case for terminal 140a. Note, too, that some of the inputs and/or outputs may not be accessible, such as output 107 of inverter 106.
Customizable logic cell 100 usually has other drawbacks, too. First, the transistors that constitute the circuit elements are typically disposed within the boundaries of a particular region. For example, region 101 confines circuit elements 102, 104, and 106 to its boundaries. A drawback to this structure is that unused space in one region is not generally used to accommodate circuit elements from another region, thereby reducing opportunities to increase circuit densities. Electronic design automation (“EDA”) tools usually require transistors that form a higher-level logic cell be limited to a certain boundary area, especially when that logic cell is part of a logic library of cells. For example, FIG. 1B shows that the transistor devices constituting circuit elements 102, 104, and 106 are formed at the semiconductor layer 174, thereby confining them to region 101. Similarly, circuit element 110 is formed at the same layer and confined to region 103. Typically, region 101 and region 103 confine placement of inputs (“A” and “B”) 180 and output (“Z”) 182, respectively, through via layer 172 up to the configuring layer 170. As such, region 101 contains inputs 180 for logic cell element (“XOR”) 152 and region 103 contains output 182 from logic cell element 154. Second, the connections formed in relation to customizable logic cell 100 and its circuit elements are manufactured using standard semiconductor manufacturing techniques that require strict adherence to predetermined design rules. A drawback to forming these connections is that the routing density is less (and conductor usage is more) than otherwise might be the case.
In view of the foregoing, it would be desirable to provide cells, systems, structures and methods that minimize the above-mentioned drawbacks and provide for a cell structure that includes independently accessible circuit elements.